(1) Field of the Invention
The invention relates to semiconductor manufacturing, and, more particularly, to a method for making planar interlevel dielectric surfaces, using chemical/mechanical polishing and a hard film to act as a polishing stop.
(2) Description of the Related Art
Semiconductor devices created on a substrate need to be connected together, which is accomplished typically by a layer of metal that contacts the devices and connects them together or to pads at the exterior surface of the chip. As the density of semiconductor devices increases, there is an increasing need to use more than one layer of metallization for interconnection. Each layer of metal is separated by an insulating layer, also referred to as an interlevel dielectric (ILD), with connections made between the layers by vias in the ILD. However, for each additional layer of metal, the top surface of the ILD layers become less and less planar, or smooth, which ultimately leads to reliability problems due to the difficulty of depositing metal on these uneven surfaces.
There is thus a need to planarize the ILD surfaces. Planarization in semiconductor manufacturing has typically been accomplished by such techniques as BPSG reflow, planarization with resist, or SOG planarization. In BPSG reflow, a layer of borophosphosilicate (BPSG) glass is deposited and then heated to a temperature of greater than 800.degree. C. The heating step causes this material to soften and flow, providing a smoother surface, as described in S.M. Sze, "VLSI TECHNOLOGY", published by McGraw-Hill Internaltional - Singapore, 1988, pages 255-257. However, the temperatures used in this process are too high if aluminum, the most common metallization material, has already been deposited on the wafer. Also, BPSG reflow is most effective for narrow indentations, that is, very small areas of the ILD surface. Broad indentations in the surface are not made planar, and thus BPSG reflow does not provide for adequate "global" planarization (planarization across the entire wafer surface).
A second planarization technique is planarization with resist or "resist etchback". One example method is described by Fujii et al in "A Planarization Technology Using a Bias-Deposited Dielectric Film and an Etch-Back Process", published in IEEE Transactions on Electron Devices, November, 1988. However, the resist etchback techniques require an increased dielectric thickness, additional process steps, and typically require that the dielectric and resist have similar etch rates, which is difficult to accomplish and control.
An example of SOG planarization is described in U.S. Pat. No. 4,676,867 by Elkins et al. This method requires the curing of a spin-on glass (SOG) layer, which converts the SOG to silicon dioxide. However, contaminants result when the structure is heated to greater than 300.degree. C., which evolve and corrode the aluminum vias.
A more recent planarization method is known as chemical/mechanical polishing, or CMP. A semiconductor wafer is held and rotated against a polishing surface, on which there is a polishing slurry containing abrasive material such as alumina or silica. At the same time, a chemical etchant may be introduced so that material is removed from the wafer by both chemical and mechanical means. U.S. Pat. Nos. 5,084,419 and 5,084,071 describe the use of CMP for providing a smooth substrate, prior to any metallization steps.
One difficulty in using CMP is determining when the planarization is complete. U.S. Pat. No. 5,036,015 describes a method to detect the planarization endpoint using the frictional difference between two materials. U.S. Pat. No. 5,081,421 describes the use of a capacitive measure of the dielectric thickness for insitu endpoint detection. U.S. Pat. No. 5,081,796 uses a laser interferometer for endpoint detection. However, these methods all require additional instrumentation to detect the completion of the chemical/mechanical polishing.